Open Hardware: RISC-V and ESP32
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RISC-V Climbs Software Mountain
Now that RISC-V has established a beachhead as a deeply embedded controller in SoCs, it’s time to start asking the next question: Can this open-source instruction-set architecture (ISA) make the next big leap into being an alternative to Arm and the x86 as a host processor?
The short answer is yes, but it could take several years and there are plenty of pitfalls along the way. Essentially, the freewheeling open-source community behind RISC-V will need to develop and adhere to a wide range of system-level standards.
So far, Nvidia and Western Digital plan to use RISC-V controllers in their SoCs, and Microsemi will use it in a new FPGA. Andes, Cortus, and startup SiFive sell IP cores, and a handful of startups plan to launch mainly machine-learning accelerators using it.
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Western Digital’s RISC-V ‘Swerv’ Core Now Available for Free
Western Digital has announced that it’s completed work on its Swerv RISC-V CPU core and has published the register-transfer level (RTL) abstraction of the design. Publishing the RTL code allows other companies to use the design.
Open-source hardware initiatives and ISAs have existed for decades, but RISC-V has gathered a critical ecosystem and corporate interests in these projects where historically there was little incentive to buy-in. The issue isn’t primarily cost savings — particularly as node sizes decrease, the licensing costs of an ARM core simply aren’t a major part of the total. The end of conventional Moore’s Law scaling has moved interest back to ISAs, as has the rise of IoT, AI, ML, and the need for new architectures to address these challenges.
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Western Digital Releases Their RISC-V Cores To The World
What grew out of a university research project is finally becoming real silicon. RISC-V, the ISA that’s completely Big-O Open, is making inroads in dev boards, Arduino-ish things, and some light Internet of Things things. That’s great and all, but it doesn’t mean anything until you can find RISC-V cores in actual products. The great hope for RISC-V in this regard looks to be Western Digital, manufacturers of storage. They’re going to put RISC-V in all their drives, and they’ve just released their own version of the core, the SweRV.
Last year, Western Digital made the amazing claim that they will transition their consumption of silicon over to RISC-V, putting one Billion RISC-V cores per year into the marketplace. This is huge news, akin to Apple saying they’re not going to bother with ARM anymore. Sure, these cores won’t necessarily be user-facing but at least we’re getting something.
As far as technical specs for the Western Digital SweRV core go, it’s a 32-bit in-order core, with a target implementation process of 28nm, running at 1.8GHz. Performance per MHz is good, and if you want a chip or device to compare the SweRV core to (this is an inexact comparison, because we’re just talking about a core here and not an entire CPU or device), we’re looking at something between a decade-old iPhone or a very early version of the Raspberry Pi and a modern-ish tablet. Again, an inexact comparison, but no direct comparison can be made at this point.
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A Network Card For The Trash-80
The idea for the trsnic comes from [Arno Puder]’s RetroStoreCard, a device that plugs into the TRS-80 Model III and connects it to a ‘personal cloud’ of sorts that hosts and runs applications without the need for cassettes or floppys. It does this with an ESP32 wired up to the I/O bus in the Model III, and it’s all completely Open Source.
[Peter] took this idea and ran with it. Thanks to the power found in the ESP32, real encrypted Internet communication can happen, and that means HTTPS and TLS.
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