Libre RISC-V M-Class
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Libre RISC-V M-Class
All of these turn out to be important for GPU workloads.
One of the most challenging aspects of Simple-V is that there is no restriction on the “redirection.” Whilst one instruction could use register five and another uses register ten, both of them could actually be “redirected” to use register 112, for example. One of those could even be changed to 32-bit operations whilst the other is set to 16-bit element widths.
Our initial thoughts advocated a standard, simple, in-order, SIMD architecture, with predication bits passed down into the SIMD ALUs. If a bit is “off,” that “lane” within the ALU does not calculate a result, saving power. However, in Simple-V, when the element width is set to 32-, 16-, or 8-bit, a pre-issue engine is required that re-orders parts of the registers, packing lanes of data together so that it fits into one SIMD ALU, and, on exit from the ALU, it may be necessary to split and “redirect” parts of the data to multiple actual 64-bit registers. In other words, bit-level (or byte-level) manipulation is required, both pre- and post-ALU.
This is complicated!
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More Details On The Proposed Simple-V Extension To RISC-V For GPU Workloads
With the proposed Libre RISC-V Vulkan accelerator aiming to effectively be an open-source GPU built atop the open-source RISC-V ISA there were recently some new details published on how the design is expected to work out.
For this very ambitious libre RISC-V SoC design. that EOMA68 developer Luke Kenneth Casson Leighton wants to pursue through crowdfunding, it's just not a matter of spinning his own RISC-V design but for making the SoC suitable for GPU workloads he has talked of a "Simple-V" extension he envisions.
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