Language Selection

English French German Italian Portuguese Spanish

RISC-V: Western Digital, Freedom and Codasip

Filed under
Hardware
OSS

More on Western Digital

  • Western Digital To Open-Source The "SweRV" RISC-V Core In 2019

    More than a year ago Western Digital talked up how they would begin designing RISC-V cores and shipping them in devices and that is indeed panning out. The company has unveiled their new SweRV core and plans to open-source it in 2019.

    At the RISC-V Summit, Western Digital talked about their continued investment into this royalty-free, open-source processor ISA. Their current RISC-V design is dubbed SweRV and is a 32-bit, 2-way super-scalar design that features a 9-stage pipeline core and clocks up to 1.8GHz and manufactured on a 28nm process. Western Digital plans to use SweRV within flash controllers / storage devices and other embedded designs.

The Libre RISC-V Vulkan Accelerator

  • The Libre RISC-V Vulkan Accelerator Will Be Targeting 25 FPS @ 720p, 5~6 GFLOPs

    For those interested in the proposed quad-core RISC-V Libre SoC that is intended to go in-step with the Rust-written Kazan for offering Vulkan support, the initial performance target has now been shared.

    While keeping in mind the Libre RISC-V effort is still very young into its endeavor, the performance target they are hoping for is 1280 x 720 25 fps, 100 Mpixels/sec, 30 Mtriangles/sec, 5-6 GFLOPs, according to their new Libre RISC-V M-Class page. Of course, that's very low by today's standards for GPUs and even for licensable graphics core IP available to embedded/mobile vendors, especially with the Libre RISC-V if everything pans out probably not premiering until 2020 at the earliest. But while the performance may be severely limited compared to what's currently available, their differentiation again is on being a "100% libre" design built atop the royalty-free RISC-V processor ISA.

Microchip

  • Microchip – RISC-V SoC FPGA architecture brings real-time to Linux allowing developers to innovate

    Microchip, via its Microsemi Corporation subsidiary, has extended its Mi-V ecosystem with a new class of SoC FPGAs. The new family joins what is claimed to be the industry’s lowest power mid-range PolarFire FPGA family with a total microprocessor subsystem based on the open, royalty-free RISC-V Instruction Set Architecture.

    The company’s new PolarFire SoC architecture brings real-time deterministic AMP capability to Linux platforms in a multi-core coherent CPU cluster. The SoC architecture, developed in collaboration with SiFive, emphasises a flexible 2MB L2 memory subsystem that can be configured as a cache, scratchpad or direct access memory. This enables designers to implement deterministic real-time embedded applications simultaneously with a rich operating system for a variety of thermal and space-constrained applications in collaborative, networked IoT systems.

    The SoC includes extensive debug capabilities incorporating instruction trace, 50 breakpoints, passive run-time configurable AXI bus monitors and FPGA fabric monitors, in addition to the company’s built-in two-channel logic analyser, SmartDebug.

PCQ Bureau

  • Industry’s first RISC-V SoC FPGA architecture brings real-time to Linux [Ed: PCQ Bureau ‘plagiarises’ a press release, edits it mildly, then pretends it’s a “news” “report” and calls itself a “news” site (filed under “NEWS”)]

    In a new era of computing driven by the convergence of 5G, machine learning and the internet of things (IoT), embedded developers need the richness of Linux-based operating systems. These must meet deterministic system requirements in ever lower power, thermally constrained design environments—all while addressing critical security and reliability requirements.

Western Digital unveils open-source SweRV RISC-V core

  • Western Digital unveils open-source SweRV RISC-V core

    Western Digital has lifted the lid on its first in-house processor, the RISC-V-based SweRV Core, which it is to release under an open source licence.

    That Western Digital has been playing with the open RISC-V instruction set architecture (ISA), using which anyone can produce a processor design without paying a penny in royalties or licensing fees, is no secret: Back in 2017 the company pledged to switch to RISC-V in its storage processing products with a view to shipping a billion cores over the following two years. It's not alone, either: Nvidia has begun transitioning away from proprietary cores to RISC-V to drive input/output in its graphics products, Rambus uses RISC-V in security parts, and it has even found its way into SSD storage controllers.

Western Digital will open source SweRV...

  • Western Digital will open source SweRV RISC-V CPU designs and tools

    On Tuesday, Western Digital, an early adopter and vocal proponent of RISC-V, announced plans to open source their implementation of the RISC-V ISA and associated development resources, providing the ability for the open source community to utilize their implementation of the architecture in their own products as well as iterate on it to meet the needs of their own products.

    SweRV Core EHX1, the first generation of RISC-V processors at Western Digital, is a 32-bit, 2-way superscalar, 9 stage pipeline core capable of clock speeds up to 1.8 GHz, produced on a 28mm CMOS process, at 4.90 CoreMark/MHz, which slightly outperforms ARM Cortex A15 (at 4.72 CoreMark/MHz). For their own products, Western Digital touts it as being fit for "embedded devices supporting data-intensive edge applications, such as storage controllers, industrial IoT, real-time analytics in surveillance systems, and other smart systems." Plans for SweRV Core will be released in Q1 2019.

RISC-V Summit Debuts to Showcase Open Source ISA

  • RISC-V Summit Debuts to Showcase Open Source ISA

    This week there's further proof that RISC-V has arrived. Something over 1,000 professionals, mostly on the hardware side of tech, are attending the first ever RISC-V Summit at the Santa Clara Convention Center in Silicon Valley.

More RISC-V

  • Saving lives with open source, RISC-V and Linux Foundations team up, and more news

    Chip designer ARM pretty much dominates the worlds of embedded systems and the Internet of Things. At least the instruction set architectures (ISA) that underlie those worlds. That could soon change thanks to the RISC-V Foundation teaming up with the Linux Foundation to "to encourage adoption of the open source RISC-V ISA."

    Although the Linux Foundation is better know for its software and IT infrastructure projects, this alliance makes sense according to Rick O’Connor, the RISC-V Foundation's executive director. O'Connor told online publication The Register that the ISA is "where software meets hardware. There's a lot of overlap in our respective ecosystems that will create a fair amount of synergy." The Linux Foundation Jim Zemlin also noted that "RISC-V is a technology that has the potential to greatly advance open hardware architecture."

Western Digital Takes A RISC

  • Western Digital Takes A RISC

    Proponents of RISC-V say that it that enables the diversity of Big Data and Fast Data applications and workloads proliferating in core data centers and in remote and mobile systems at the edge. It provides an alternative to current, standard, general purpose compute architectures. With RISC-V, open standard interfaces can be utilized to enable specialty processing, memory centric solutions, unique storage and flexible interconnect applications. The RISC-V Foundation has a broad ecosystem represented by the significant increase in attendees at the 2018 Summit compared to 2017.

Comment viewing options

Select your preferred way to display the comments and click "Save settings" to activate your changes.

More in Tux Machines

Graphics: Red Hat's Wayland Agenda and AMD Begins Queueing Graphics Driver Changes For The Linux 5.3 Kernel

  • Hans de Goede: Wayland itches summary
    1. Middle click on title / header bar to lower the Window does not work for native apps. Multiple people have reported this issue to me. A similar issue was fixed for not being able to raise Windows. It should be easy to apply a similar fix for the lowering problem. There are bugs open for this here, here and here. 2. Running graphical apps via sudo or pxexec does not work. There are numerous examples of apps breaking because of this, such as lshw-gui and usbivew. At least for X11 apps this is not that hard to fix. But sofar this has deliberately not been fixed. The reasoning behind this is described in this bug. I agree with the reasoning behind this, but I think it is not pragmatic to immediately disallow all GUI apps to connect when run as root starting today.
  • Hans de Goede: Better support for running games under Wayland (with GNOME3/mutter as compositor)
    First of all I do not want people to get their hopes up about $subject of this blogpost. Improving gaming support is a subjects which holds my personal interest and it is an issue I plan to spend time on trying to improve. But this will take a lot of time (think months for simple things, years for more complex things).
  • AMD Begins Queueing Graphics Driver Changes For The Linux 5.3 Kernel
    Being past the Linux 5.2 kernel merge window, AMD's open-source Linux graphics driver developers have already begun queuing changes anticipated for Linux 5.3 via a work-in-progress tree. Given the short time that this 5.3 WIP tree has been around, there isn't too much exciting about the changes -- yet. But surely over the weeks ahead it will get interesting. Making things particularly interesting is that we are expecting initial Navi support to make it for Linux 5.3... In recent weeks AMD began pushing AMDGPU LLVM compiler back-end changes for GFX10/Navi and we expect the AMDGPU DRM kernel driver enablement to come for Linux 5.3. Linux 5.3 will already be arriving after the rumored release of the first Navi graphics cards so having to wait past 5.3 for mainline support would already be tragic. But given the recent LLVM activity, we expect AMD to push out the Navi kernel driver changes soon. For that likely massive patch-set to be reviewed in time, the Navi patches would need to make their debut within the next few weeks.

today's howtos and programming

Fedora 30 Workstation review - Smarter, faster and buggier

Fedora 30 is definitely one of the more interesting releases of this family in a long-time. It brings significant changes, including solid improvements in the desktop performance and responsiveness. Over the years, Fedora went from no proprietary stuff whatsoever to slowly acknowledging the modern needs of computing, so now it gives you MP3 codecs and you can install graphics drivers and such. Reasonable looks, plus good functionality across the board. However, there were tons of issues, too. Printing to Samba, video screenshot bug, installer cropped-image slides, package management complications, mouse cursor lag, oopses, average battery life, and inadequate usability out of the box. You need to change the defaults to have a desktop that can be used in a quick, efficient way without remembering a dozen nerdy keyboard shortcuts. All in all, I like the freshness. In general, it would seem the Linux desktop is seeing a cautious revival, and Fedora's definitely a happy player. But there are too many rough edges. Well, we got performance tweaks after so many years, and codecs, we might get window buttons and desktop icons one day back, too. Something like 6/10, and definitely worth exploring. I am happy enough to do two more tests. I will run an in-vivo upgrade on the F29 instance on this same box, and then also test the distro on an old Nvidia-powered laptop, which will showcase both the support for proprietary graphics (didn't work the last time) and performance improvements, if they scale for old hardware, too. That's all for now. Read more

Events: Automotive at LF, Linux Clusters Institute, Linux Plumbers Conference (LPC)

  • Automotive Linux Summit and Open Source Summit Japan Keynote Speakers and Schedule Announced
    The Linux Foundation, the nonprofit organization enabling mass innovation through open source has announced the speaker line up for Open Source Summit Japan and Automotive Linux Summit. One registration provides access to all content at both events, which will be held July 17-19 at the Toranomon Hills Forum in Tokyo. Open Source Summit Japan (OSSJ) and Automotive Linux Summit (ALS) will bring together top talent from companies on the leading edge of innovation including Toyota Motor Corporation, Uber, Intel, Sony, Google, Microsoft and more. Talks will cover a range of topics, with ALS talks on everything from infrastructure and hardware to compliance and security; and OSSJ sessions on AI, Linux systems, cloud infrastructure, cloud native applications, open networking, edge computing, safety and security and open source best practices.
  • Register Now for the 2019 Introductory Linux Clusters Institute Workshop
    Registration is now open for the 2019 Linux Clusters Institute (LCI) Introductory Workshop,which will be held August 19-23, 2019 at the Rutgers University Inn & Conference Center in New Brunswick, NJ. This workshop will cover the fundamentals of setting up and administering a high-performance computing (HPC) cluster and will be led by leading HPC experts.
  • Additional early bird slots available for LPC 2019
    The Linux Plumbers Conference (LPC) registration web site has been showing “sold out” recently because the cap on early bird registrations was reached. We are happy to report that we have reviewed the registration numbers for this year’s conference and were able to open more early bird registration slots. Beyond that, regular registration will open July 1st. Please note that speakers and microconference runners get free passes to LPC, as do some microconference presenters, so that may be another way to attend the conference. Time is running out for new refereed-track and microconference proposals, so visit the CFP page soon. Topics for accepted microconferences are welcome as well.